Search - RISC CPU

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[Other resource] 靳远－源程序 DL : 0: 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
Date : 2008-10-13 Size : 433kb User : core_design
[Other resource] embedded_risc DL : 0: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Date : 2008-10-13 Size : 125.6kb User : 箫勇天
[VHDL-FPGA-Verilog] alu DL : 0: mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
Date : 2025-07-06 Size : 4kb User : yzhang
[VHDL-FPGA-Verilog] RISC_SPM DL : 0: 简单risc cpu设计，本人通过书中的代码，又加了一些，已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
Date : 2025-07-06 Size : 121kb User : 王迪
[VHDL-FPGA-Verilog] cpu-design DL : 0: VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
Date : 2025-07-06 Size : 2.75mb User : lzy
[VHDL-FPGA-Verilog] zxcpu DL : 0: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Date : 2025-07-06 Size : 1.03mb User : zhaoshu
[VHDL-FPGA-Verilog] A-RISC-Design DL : 0: RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
Date : 2025-07-06 Size : 1.08mb User : 梁梁
[VHDL-FPGA-Verilog] cpu DL : 0: 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
Date : 2025-07-06 Size : 19kb User : qc
[VHDL-FPGA-Verilog] RISC_cpu DL : 0: 基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
Date : 2025-07-06 Size : 257kb User : 西门吹雪
[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP DL : 1: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Date : 2025-07-06 Size : 33kb User : 张秋光
[VHDL-FPGA-Verilog] RISC-CPU DL : 1: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Date : 2025-07-06 Size : 3mb User : vice
[VHDL-FPGA-Verilog] RISC---8 DL : 0: 集成RISC-CPU芯片设计，很实用的程序，对初学FPGA的同学有很大的帮助奥-Integrated RISC-CPU chip design, very practical program, beginner FPGA classmates help Austrian
Date : 2025-07-06 Size : 191kb User : 天空
[VHDL-FPGA-Verilog] cpu-risc DL : 0: wb_switch，cpu设计，精简指令cup设计-wb_switch，opencore，risc cpu design。
Date : 2025-07-06 Size : 36kb User : 浮萍
[source in ebook] 16-CISC-CPU-design DL : 0: 16位精简指令集的CPU设计，有完整的步骤和原程序可供学习-16-bit RISC CPU design, complete steps and the original program for learning
Date : 2025-07-06 Size : 683kb User : 何宗苗
[VHDL-FPGA-Verilog] 8Bit-CPU DL : 0: 8 Bit RISC CPU implementation in VHDL
Date : 2025-07-06 Size : 5kb User : Mufossa
[VHDL-FPGA-Verilog] CPU DL : 0: 4位精简指令集的cpu设计，是数字电路与逻辑的课程设计，对于学习微处理器和数字电路的同学还是很有帮助的-4 RISC cpu design, digital circuit and logic of curriculum design, microprocessors and digital circuits for learning or helpful for students
Date : 2025-07-06 Size : 3.85mb User : lu
[OS Develop] RISC-CPU- DL : 0: 用VHDL语言实现32位CPU的各种运算功能，熟悉32位CPU各模块的工作原理，熟悉流水线数据通路和控制单元的工作原理从而熟悉CPU的工作机理。-Mac circuit realization
Date : 2025-07-06 Size : 11.17mb User : 卓丽媛
[VHDL-FPGA-Verilog] Mini-Risc-core DL : 0: 这个源码是RISC型CPU处理器，正常动作，给很大帮助想做CPU处理器的人。-This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the PIC 16C57 Microchip.
Date : 2025-07-06 Size : 101kb User : 金铁男
[VHDL-FPGA-Verilog] cpu DL : 0: 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Date : 2025-07-06 Size : 7kb User : 耿瑞
[Other] riscCPU DL : 0: 实现八位RISC cpu 含有V文件和 testbents测试文件(Realization of eight bits RISC cpu)
Date : 2025-07-06 Size : 6.44mb User : 理大人

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